1. Field of the Invention
This invention relates generally to the synchronization of periodic signals, such as clock signals. More particularly, the invention relates to a method and apparatus for characterizing a delay locked loop.
2. Description of the Related Art
Many high speed electronic systems possess critical timing requirements that dictate the need to generate a periodic clock waveform possessing a precise timing relationship with respect to some reference signal. The improved performance of computing integrated circuits and the growing trend to include several computing devices on the same board present a challenge with respect to synchronizing the time frames of all the components.
While the operation of all components in the system should be highly synchronized, i.e., the maximum skew in time between the significant edges of the internally generated clocks of all the components should be minimized, it is not enough to feed the reference clock of the system to all the components. This is because different chips may have different manufacturing parameters, which, when taken together with additional factors such as ambient temperature, voltage, and processing variations, may lead to large differences in the phases of the respective chip generated clocks.
Conventionally, synchronization is achieved by using digital delay locked loop (DDLL) circuits to detect the phase difference between clock signals of the same frequency and produce a digital signal related to the phase difference. By feeding back the phase difference-related signal to control a delay line, the timing of one clock signal is advanced or delayed until its rising edge is coincident with the rising edge of a second clock signal.
The performance of DDLL circuits is typically tested by measuring the alignment between the data output by the device and the external reference clock to which the data is to be synchronized. FIG. 1A is a timing diagram showing a reference clock signal 10 and a data output signal 20. If the performance of the DDLL were ideal, the data signal would transition exactly in synch with the edge of the clock signal. However, because the DDLL is implemented using digital circuitry, it must make discrete delay adjustments to attempt to synchronize the data transitions with the reference clock signal. Because of this granularity, there is typically some degree of skew between the reference clock signal and the transitions of the data signal. The skew present between transitions of the reference clock and data transitions is typically referred to as an access time, tAC. The tAC may be positive (i.e., the data signal transitions after the transition of the reference clock signal), as shown in FIG. 1, or negative (i.e., the data signal transitions before the transition of the reference clock signal).
Typically, the specifications for digital devices, such as synchronous dynamic random access memories (SDRAM), specify a tolerance value for maximum and minimum tAC values, such as xc2x1750 picoseconds. To test the performance of the completed device, a back-end test is performed to characterize the response of the DDLL circuit by measuring tAC. To measure tAC the device is typically subjected to a performance test. The skew between the reference clock signal and the data transitions are measured in a test unit to establish a tAC(min) and a tAC(max) for the device.
The tAC characterization test may be used for fault detection and/or tuning. For a fault detection screening, a device that fails the criteria for tAC may be scrapped. If the device is unable to keep the data transitions within the predetermined tolerances, other devices may receive errant data (i.e., data that is still transitioning when it is expected to be stable).
Even if a particular test results in a tAC failure, it may still be possible to tune the DDLL to place the tAC within tolerances. Indeed, even for devices that pass the tAC it is common to tune the DDLL to improve its performance. Small shifts in the delay imposed by the DDLL circuit may be implemented by changing the state of various fuses and anti-fuses in the circuit. A prerequisite to accurate tuning is the presence of an accurate tAC characterization.
There are limitations to the accuracy of the tAC characterization performed using the back-end test methodology described above. Due to the number of devices being tested, it is necessary to perform the testing quickly. Typically, the entire test may be performed with the device operating at a near constant temperature and voltage. Variations in the process, voltage, and temperature (i.e., PVT variations) can cause changes in the performance of the DDLL, because they affect the delay imposed by the delay line. For example, increases in temperature may increase the delay imposed by the delay line.
Typically, a delay line is comprised of an array of serially cascaded delay elements that are selectively engaged by a control circuit to synchronize the data transitions with the reference clock. During operation of the DDLL circuit, a phase detector monitors phase errors between the reference clock signal and the internal clock signal used to control the data transitions and adds or removes the discrete delay elements to reduce the phase errors measured by the phase detector. The control is thus granular in nature due to the discrete nature of the stages in the delay line.
FIGS. 2A through 2C are diagrams illustrating operating bands 30 of a DDLL circuit. The bands 30 correspond to discrete stages of the delay line in the DDLL circuit. The DDLL represented by the diagrams of FIGS. 2A through 2C is designed to operate with three possible bands 30. Note that ideal bands 30 are illustrated without any additional noise. Also note that if the hysteresis of the DDLL (i.e., dead band) is larger, even more bands 30 may exist.
During the tAC characterization test, the tester only measures the bands 30 in which the device is operating. Because parameters such as voltage and temperature are not varied during the test, it is possible that the tester does not accurately characterize the worst case tAC. Such PVT variation could cause the DDLL to actually shift to different bands 30, which would broaden out the actual tAC. A worst case tAC may be determined in the lab by probing a signal pin, varying PVT conditions, such as temperature, and monitoring the device over time using an oscilloscope. This test reveals the full banding plus noise characteristics of the DDLL. Such a characterization in the lab is time consuming and not practical for back-end testing of large numbers of devices.
Exemplary characterization errors are illustrated in FIGS. 2A through 2C. If the PVT conditions were varied in a lab setting, operation in all three bands 30 could be observed and the proper values for tAC(min) and tAC(max) could be determined. However, under the conditions of the back-end test, all three bands 30 may not be observed. FIG. 2A represents the case where the back-end characterization test observes the DDLL operating in only one band 30. The tester thus characterizes tAC(min) and tAC(max) as indicated. FIG. 2B represents the case where operation is observed in two bands 30, resulting in a different characterization, albeit still inaccurate. FIG. 2C represents the case where operation is observed in all three bands, and an accurate characterization can be made.
If the conditions represented by FIGS. 2A or 2C are observed during the back-end test, the tAC characterization produced by the tester will be incorrect. This inaccurate characterization may lead to passing devices that are actually not within design tolerances. Characterization errors may also result in incorrect decisions regarding which DLL trim fuses should be blown to move the entire tAC window and tune the DDLL. If the actual tAC is different than the back-end characterization, the window may be shifted too far or even in the wrong direction. Such an errant tuning could cause a device that was initially within design tolerances to be moved to a region where it is actually outside of these tolerances.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a delay locked loop including a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal. The feedback path is configured to provide a feedback clock signal based on the output clock signal. The phase detector is configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal. The logic is coupled to the delay line and configured to receive the shift signal and control the time interval based on the shift signal. The dither circuit is coupled to the delay line and configured to introduce a delay responsive to an assertion of a test mode enable signal.
Another aspect of the present invention is seen in a method for synchronizing clock signals. The method includes receiving an input clock signal. The input clock signal is delayed by a time interval to generate an output clock signal. A feedback clock signal based on the output signal is received. A phase alignment error between the input clock signal and the feedback clock signal is detected. The time interval is controlled to synchronize the input clock signal with the feedback clock signal. A delay in one of the input clock signal and the feedback clock signal is introduced responsive to a test mode enable signal.